`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:25:40 10/31/2012 
// Design Name: 
// Module Name:    DETECT_UNIT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module STRENGTH_DETECT_UNIT #(parameter LOG_LEN=5, LEN=32, WIDTH=33, TRES=0)
(

	 input clk,
	 input rst,
    input signed [WIDTH-1:0] in,
    output reg detect
    );

	 
	 reg[LOG_LEN-1:0] count;
	 reg signed[WIDTH-1:0] fifo[0:LEN-1];
	 reg signed[WIDTH+LOG_LEN-1:0] sum;
	 integer i;
			
			
	always @(posedge clk or negedge rst)
		if(!rst)
			sum <= 0;
		else
			sum <= sum - fifo[LEN-1] + fifo[0];
			
	
	always @(posedge clk or negedge rst)
		if(!rst)
		begin
			detect <= 0;
			count <= 0;
		end
		else if(sum > TRES)
		begin
			detect <= 1;
			count <= 1;
		end
		else if(count == 32)
		begin
			detect <= 0;
			count <= 0;
		end
		else if(count > 0)
		begin
			detect <= 1;
			count <= count + 1;
		end
		else
		begin
			detect <= 0;
			count <= 0;
		end
			
	 
	always @(posedge clk or negedge rst)
		if(!rst)
			for (i=0; i<LEN; i=i+1)
				fifo[i] <= 0;
		else
			begin
			for (i=1; i<LEN; i=i+1)
				fifo[i] <= fifo[i-1];
			fifo[0] <= in;
			end
				
				
endmodule
